SystemVerilog is a Hardware Description Language (HDL), which is what the first step in the process. The HDL synthesis is the level just above the part of the process where the major tooling issues referenced exist, since synthesis generally isn't specific to a particular chip vendor and, as noted, is also a necessary step before laying out an ASIC.
Several friends complain about the arcane nature of verilog and vhdl and like the idea of better languages written by actual language designers. But since the steps of FPGA compiling first converts the HDL language into a netlist which is used for all other operations, once a tool chain exists we can just replace the verilog compiler with a VHDL or bluespec compiler and everything will still work.
