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But memory is latency-limited, not bandwidth-limited. The channels are idle quite a lot of the time.

So you go from

  REQUEST1---------RESPONSE1-REQUEST2---------RESPONSE2
to

  REQUEST1---------RESPONSE1RESPONSE1
  REQUEST2---------RESPONSE2RESPONSE2
Each request individually is slightly slower, but the total bandwidth is greatly increased.


I think SDRAM can do

    REQUEST1-REQUEST2---RESPONSE1-RESPONSE2
can't it?


Yes it can! But, unless I'm mistaken, only within the same bank. This means you can basically only do this for sequential access, not random access. And there's still a non-zero latency between the responses, so it's still slightly slower than doubling the channels.




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